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Accenture adzuna.in

Design-For-Test (DFT) Engineer

Open · checked 2h ago Via Adzuna Check first Full-time Posted 2h ago

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Pay
Not disclosed
Where
India
Who
Any batch ·

Work as a Design-For-Test Engineer at Accenture enabling effective post-manufacturing chip testing by integrating testability features during the design phase.

Design for Testability (DFT)scan chainsBuilt-In Self-Test (BIST)boundary scan

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    Likely interview questions

    1. Can you explain how scan chains are implemented in integrated circuits?
    2. What is the role of Built-In Self-Test (BIST) in chip testing?
    3. How do you collaborate with verification teams to optimize test coverage?
    Skip this one if: Skip if you do not have background or skills in Design for Testability (DFT) and semiconductor chip testing.

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