Physical Design Engineer- Static Timing Analysis (STA)

Work as a Physical Design Engineer focusing on Static Timing Analysis for high-resiliency mainframes and hybrid cloud platforms at IBM.

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Technical

1. What is setup and hold time violation and how do you fix them in STA?
2. Explain the concept of crosstalk delay and noise in physical design.
3. What are on-chip variation (OCV) and derating factors in static timing analysis?

Scenario

1. What would you do if a critical timing path fails to meet the required frequency after routing?
2. How would you approach debugging a high number of hold violations discovered post-clock tree synthesis?

HR

1. Tell me about a time you had to collaborate with a team to solve a complex engineering problem.
2. How do you handle tight project deadlines while maintaining high accuracy in your design analysis?

About IBM

1. How does IBM Infrastructure & Technology contribute to hybrid cloud and mainframe systems?

Practice questions written from the job listing, not this company's real interview questions.

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